NI-VISA is recommended because of the following three advantages.
NI-VISA uses many of the same operations to communicate with instruments, regardless of the interface type. This makes it easy to switch interfaces and provides a single language to learn for multiple different instruments. For example, the VISA command to write an ASCII string to a message-based instrument is the same whether the instrument interface is serial, GPIB, or USB.
NI-VISA is designed so that programs written using VISA function calls can move from one platform to another. VISA does this by defining its own data types. This ensures your application performs consistently across different platforms. Therefore, a VISA application written in LabVIEW can be easily ported to any platform that supports LabVIEW. NI-VISA supports several operating systems, including Windows OS versions, MacOS versions, and Linux distributions.
NI-VISA is an extremely easy interface to learn. It provides an API that has bus-independent functions for most of its I/O functionality. The most used functionality for instrumentation is provided in a compact command set, eliminating the need to learn low level communication protocols for multiple interface types.
Figure 3. NI USRP-
Following a common SDR architecture, USRP hardware implements a direct conversion analog front end with high-speed analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) featuring a fixed-personality FPGA for the digital downconversion (DDC) and digital upconversion (DUC) steps. The receiver chain begins with a highly sensitive analog front end that can receive very small signals and digitize them using direct downconversion to in-phase (I) and quadrature (Q) baseband signals. Downconversion is followed by high-speed analog-to-digital conversion and a DDC that reduces the sampling rate and packetizes I and Q for transmission to a host computer using Gigabit Ethernet for further processing. The transmitter chain starts with the host computer where I and Q are generated and transferred over the Ethernet cable to the USRP hardware. A DUC prepares the signals for the DAC after which I-Q mixing occurs to directly upconvert the signals to produce an RF frequency signal, which is then amplified and transmitted.
Figure 4. USRP- System-Level Diagram
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Figure 5. NI USRP RIO
USRP RIO combines two full-duplex transmit and receive channels with up to 160 MHz/channel of real-time bandwidth and a large DSP-oriented Kintex-7 FPGA in a half-1U rack-mountable form factor. The analog RF front end interfaces with the large Kintex-7 410T FPGA through dual ADCs and DACs clocked at 120 MS/s.
Each RF channel includes a switch allowing for time division duplex (TDD) operation on a single antenna using the TX 1 RX1 port, or frequency division duplex (FDD) operation using two ports, TX1 and RX2.
The USRP RIO devices cover from 50 MHz to 6 GHz frequency range with user-programmable digital IO lines for controlling external devices. The Kintex-7 FPGA is a reconfigurable LabVIEW FPGA target that incorporates DSP48 coprocessing for high-rate, low-latency applications. The PCI Express x4 connection back to the system controller allows up to 800 MB/s of streaming data transfer back to your desktop or PXI chassis, and 200 MB/s to your laptop. This connection allows up to 17 USRP RIO devices to be cabled back to a single PXI Express chassis, which can then be daisy chained together for high-bandwidth, high-channel-count applications.
Figure 6. USRP- System-Level Diagram
Figure 7. NI USRP-
The stand-alone USRP RIO includes an onboard processor, FPGA, and RF all in one form factor. The USRP- is built on a heterogeneous processing architecture with an onboard Intel Core i7 processor running the NI Linux Real-Time OS. It is a 2x2 radio that covers frequencies between 10 MHz and 6 GHz with the 160 MHz bandwidth and adds an x86 processor to form stand-alone system operation, which can be targeted to deterministically perform processing and program the Xilinx Kintex 470 FPGA all from a single design environment. The USRP- is also equipped with a GPS-disciplined 10 MHz oven-controlled crystal oscillator (OCXO) Reference Clock.
Figure 8. USRP- System-Level Diagram
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